Field of the Invention
The invention relates to a method for fabricating a semiconductor memory device.
In modern semiconductor memory devices, in particular, in chain FeRAM memories or the like, a plurality of capacitor devices are provided as storage elements in the form of a capacitor configuration in the region of a semiconductor substrate or the like and/or of a passivation region and/or of a surface region thereof.
An objective of the ongoing development of modern semiconductor memory technologies is, inter alia, the formation of the most extensive integration density possible. Conventional semiconductor memory devices that use capacitor devices as storage elements are limited with regard to the integration density to the effect that the capacitor devices used should not fall below a certain minimum size, and, thus, a minimum lateral extent, for their functioning as storage capacitors or storage elements. Consequently, even with minimum distance separating conventional capacitor devices, there is a resultant limit in the area density of storage elements that cannot be undershot. In this case, the respective minimum separating distance is given in each case by the minimum feature size of the respective lithographic technique.
It is accordingly an object of the invention to provide a method for fabricating a semiconductor memory device that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that achieves a particularly high integration density in conjunction with functional reliability.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method for fabricating a semiconductor memory device. The method includes, forming semiconductor substrate, a passivation region, and/or a surface region with a CMOS structure. A capacitor configuration of a plurality of capacitor devices serving as storage elements is formed in a region of the semiconductor substrate, the passivation region, and/or the surface region. Respective capacitor devices are formed and/or patterned partially and/or locally in a substantially vertically extending fashion with respect to the horizontally extending semiconductor substrate, the passivation region, and/or the surface region, and, as a result, forming and/or patterning a three-dimensional configuration extending partially and/or locally into a third dimension with respect to the semiconductor substrate, the passivation region, and/or the surface region for a respective one of the capacitor devices. A contact connection of the capacitor devices and of the electrode devices is formed with the CMOS structure by plug regions after production of the capacitor devices. Preferably, the method fabricates a chain FeRAM memory.
In the method for fabricating a semiconductor memory device, in particular, a chain FeRAM memory or the like, firstly a semiconductor substrate or the like, a passivation region, and/or a surface region thereof with a CMOS structure are formed. Such a configuration is fundamental for the circuit of the semiconductor memory device. Furthermore, a capacitor configuration of a plurality of capacitor devices serving as storage elements is formed in the region of the semiconductor substrate or the like, the passivation region, and/or the surface region thereof.
Furthermore, in accordance with another mode of the invention, the capacitor device is respectively formed and/or patterned in a fashion extending at least partially and/or locally substantially vertically or perpendicularly to the substrate with respect to the, in particularly, substantially horizontally extending, semiconductor substrate or the like, the passivation region, and/or the surface region thereof. Furthermore, it is provided according to the invention that, as a result, in particular, in each case a substantially three-dimensional configuration or structure and/or an configuration or structure extending at least partially and/or locally substantially into the third dimension with respect to the, in particular, substantially horizontally extending, semiconductor substrate or the like, the passivation region, and/or the surface region thereof, is formed and/or patterned for the respective capacitor device.
It is, thus, a fundamental idea of the method according to the invention to form and/or to pattern the respective capacitor devices such that they run substantially in vertically extending fashion with respect to the surface of the semiconductor substrate or the like. What is thereby achieved is that the integration density and, thus, the area of the entire cell array is no longer dominated by the required area proportion of the electrode areas, but rather ultimately substantially by the resolution and the feature size of the patterning method during the formation of the capacitor configuration. In principle, the possibility is, thus, afforded of orienting the feature size or minimum lateral extent of a capacitor device to the physically required layer thicknesses for the capacitor electrodes and the dielectric.
In such a case, a first and a second electrode device and also a dielectricxe2x80x94substantially provided between the latterxe2x80x94of the respective capacitor device are respectively formed and/or patterned at least partially and/or locally in a fashion extending substantially vertically or perpendicularly to the substrate with respect to the, in particular, substantially horizontally extending, semiconductor substrate or the like, the passivation region, and/or the surface region thereof. This is done such that, in this case, in particular, the sequence of first electrode device, dielectric, and second electrode device of the respective capacitor device is formed at least partially and/or locally in substantially horizontally extending fashion with respect to the, in particular, substantially horizontally extending, semiconductor substrate or the like, the passivation region and/or the surface region thereof, in a form disposed one beside the other in the surface region of the semiconductor substrate and/or of the passivation region thereof.
In the text above and below, the term dielectric always means the central dielectric of the storage capacitor/the capacitor device and/or the so-called node dielectric. This is, in particular, a ferroelectric (SBT, PZT, . . . ), a paraelectric, or the like.
In accordance with a further mode of the invention, the, in particular, substantially horizontally extending, semiconductor substrate or the like, and/or the surface region thereof and, in particular, the CMOS structure are at least partially covered and/or embedded by at least one first substantially top-situated and/or substantially laterally extending passivation region made of a substantially electrically insulating material, in a two-dimensional, large- and/or whole-area manner and/or with a planar surface region. Such a measure creates an isolation between the actual semiconductor substrate and the CMOS structure formed therein, and the capacitor configuration that is to be disposed thereabove. The passivation region is deposited, in particular, in a substantially two-dimensional, large- and/or whole-area manner and/or, in particular, with a planar surface.
In accordance with an added mode of the invention, a contact connection for the capacitor devices to be formed and particularly for their electrode devices to be formed with the CMOS structure is formed by contact regions or plug regions substantially after the formation of the capacitor devices.
In accordance with an additional mode of the invention, at defined first regions and/or at defined first locations in the first, substantially top-situated, passivation region, cutouts are formed, in particular, by a, preferably selective, etching process or the like and/or, in particular, in a manner spaced apart substantially vertically from the level of the semiconductor substrate and/or of the surface region thereof. In such a case, in particular, substantially electrically insulating elevated regions are formed in the first passivation region at second defined regions or locations between the first defined regions or locations.
Regions substantially above and between source/drain regions of selection transistor devices provided in the surface region of the semiconductor substrate and/or substantially between defined second regions or locations of contact regions or plug regions to be provided for the contact connection of the capacitor configuration to be formed with the CMOS structure of the semiconductor substrate or the like and/or of the surface region thereof are chosen, in particular, as defined first regions or as defined first locations.
In accordance with yet another mode of the invention, the cutouts are formed vertically from the level of the surface region of the semiconductor substrates, and, in particular, from the level of source/drain regions, gate and/or word line regions of selection transistor devices provided.
Furthermore or as an alternative, in accordance with yet a further mode of the invention, the cutouts are formed laterally at least partially at least as far as edge regions of plug regions or contact regions to be provided. In addition, it is provided in such a case that, as a result, edge regions of the cutouts formed are provided as edge regions of the plug regions or contact regions to be provided. What is achieved by these measures is that the edges or walls of the cutouts simultaneously form edges or walls of the plugs to be provided. This is particularly advantageous with regard to the configuration of the contact connection with the electrode devices.
Afterward, in accordance with yet an added mode of the invention, at least one material region for the electrode devices is then deposited. This is done, in particular, using at least one substantially electrically conductive material, for example, a metal, a metal oxide, and/or the like. Furthermore, the material region for the electrode devices is preferably deposited in a conformal manner, in the form of a two-dimensional deposition technique, in a large- and/or whole-area manner, in particular, edge regions of the cutouts and/or the elevated regions being lined and/or covered.
Consequently, by the measures outlined above, the capacitor configuration with the plurality of capacitor devices is fundamentally pre-patterned, a contact connection of the electrode devices of the capacitor devices with the plug regions and the CMOS structure formed underneath being inherently ensured.
In such a case, an isolation of the electrode devices that are not to be contact-connected may optionally be necessary. This is realized, in particular, by virtue of the fact that at least substantially laterally extending regions of the material region for the electrode devices are eroded and removed to the level, in particular, by an anisotropic etching-back or the like.
As a result, in particular, substantially vertically extending regions are formed adjacent to the insulating elevated regions. These vertically extending regions of substantially electrically conductive material then form the electrode devices of the capacitor devices.
In accordance with yet an additional mode of the invention, if appropriate, the barrier and/or insulation region for the dielectric is respectively formed in a plurality of layers. In addition or as an alternative it is provided that the barrier and/or insulation region for the dielectric is formed in a topmost regionxe2x80x94substantially remote from the semiconductor substrate or the likexe2x80x94and/or the surface region thereof in each case as nucleation layer for the dielectric that is subsequently to be applied.
In accordance with again another mode of the invention, on lateral bottom regions or the like of the cutouts, in each case a barrier and/or insulation region for the dielectric to be provided is formed, in particular, by specific and/or anisotropic, that is to say, substantially directed, deposition, and/or, in particular, using at least one substantially electrically insulating material.
The barrier and/or insulation region for the dielectric may also be deposited before the elevated plugs, followed by an etching step with a stop on the nucleation layer. Conformal deposition onto the elevated plugs is appropriate as an alternative.
Furthermore, preference is attached to the fact thatxe2x80x94in particular, on the respective barrier and/or insulation region for the dielectricxe2x80x94a material region for the dielectric is deposited, in particular, in the form of a ferroelectric, a material that forms a ferroelectricxe2x80x94in particular, following an annealing process, or the like, in particular, in a two-dimensional form, conformal form, large-area form, whole-area form and/or a form that fills the first cutouts as far as the level of the surface region of the first passivation region, and/or by subsequent polishing as far as the level of the surface region of the first passivation region. This is done, in particular, to form a respective region for the dielectric between the electrode devices.
Afterward, in accordance with again a further mode of the invention, the material layer for the dielectric and/or the dielectric may be subjected to a heat treatment process, in particular, at elevated temperature and/or in a defined process atmosphere, which contains, in particular, oxygen or the like, to be precise without damaging the regions below the layer for the barrier and/or insulation region for the dielectric.
In accordance with again an added mode of the invention, second cutouts are formed at the defined second regions or the defined second locations, in particular, above the source/drain regions of the selection transistor devices. This is done, in particular, by a, preferably selective, etching process or the like. In such a case, in particular, the substantially electrically insulating elevated regions are substantially removed such that side regions or edge regions of the electrode devices are uncovered at least in part.
Furthermore, in this case, in particular, the barrier region and also the first passivation region in the region of the second defined locations or second defined regions are eroded as far as the level of the surface region of the semiconductor substrate such that the surface region of the source/drain regions is uncovered in each case.
This has the advantage, in particular, in accordance with again an additional mode of the invention, that a material region of a substantially electrically conductive material can be deposited, to be precise, optionally after formation of a liner or the like and/or optionally after formation of a hard mask that protects the ferroelectric, in particular, in a two-dimensional form, conformal form, large-area form, whole-area form, and/or a form that fills the second cutouts in each case as far as the level of the surface region of the source/drain regions, and/or by optional subsequent polishing or the like as far as the level of the surface regions of the electrode devices and/or of the dielectric or optionally as far as the hard mask. In such a case, it is provided, in particular, that, as a result, first electrode devices or second electrode devices that are opposite one another in the second cutouts are in substantially electrically conductive contact together with the respective source/drain regions.
In accordance with still another mode of the invention, at least some of the capacitor devices are contact-connected by their respective first electrode device through a first contact element to the first electrode device of a first substantially electronically adjacent capacitor device and by their second electrode device through a second contact element to the second electrode device of a second substantially directly spatially adjacent capacitor device of the capacitor configuration, in order to form a capacitor configuration with an at least partly connected or chain structure. In this case, it is furthermore provided, in particular, that the first electrode devices that are contact-connected to one another and/or the second electrode devices are in each case formed as a substantially contiguous and/or integral or one-part electrically conductive region. This is done, in particular, together with a respective first contact element or the like and/or, in particular, in each case together with a plug region or contact region or the like.
In the case of the device, it is provided that, in particular, in chain FeRAM memories or the like, the capacitor device is respectively formed in a fashion extending at least partially and/or locally substantially vertically or perpendicularly to the substrate with respect to the, in particularly substantially horizontally extending, semiconductor substrate or the like, the passivation region, and/or the surface region thereof, and that, as a result, in particular, in each case a substantially three-dimensional configuration or structure and/or an configuration or structure extending at least partially and/or locally substantially into the third dimension with respect to the, in particular, substantially horizontally extending, semiconductor substrate or the like, the passivation region, and/or the surface region thereof, is formed for the respective capacitor device.
It is, thus, a central concept of the present invention to vertically orient the storage capacitors of the capacitor configuration of the semiconductor memory devicexe2x80x94in contrast to the conventional configuration in which the capacitor devices are formed horizontally or in laterally extending fashion. Specifically, the area of the respective capacitor device is then determined and given, not by the electrode areas, but rather ultimately by the respective layer thicknesses that are required for the electrode devices and for the dielectric. This means that a further increase in the integration density can be achieved, because the required area proportions for the electrodes and for the dielectric are provided by the three-dimensional patterning.
In such a case, the respective capacitor devices in each case have a first electrode device, a second electrode device and a dielectric substantially provided between the latter.
In an advantageous manner, the capacitor device is in each case formed as a stack structure or has such a structure, thereby resulting in a particularly compact construction, which can only be realized in an inadequate manner in the case of an offset structure.
It is provided, in particular, that the electrode device and/or the dielectric of the respective capacitor device are formed at least partially and/or locally in a fashion extending substantially vertically or perpendicularly to the substrate in each case with respect to the, in particular, substantially horizontally extending, semiconductor substrate or the like and/or with respect to an insulation region or passivation region and/or with respect to the surface region thereof. In this case, it is provided, in particular, that the sequence of first electrode device, dielectric, and second electrode device of the respective capacitor device is formed at least partially and/or locally in substantially horizontally extending fashion with respect to the, in particular, substantially horizontally extending, semiconductor substrate or the like and/or with respect to an insulation region or passivation region and/or with respect to the surface region thereof, in particular, in a form disposed one beside the other in the surface region of the semiconductor substrate or the like and/or of an insulation region or passivation region thereof. In accordance with this measure, it is provided, then, that the sequence of the electrode devices and the dielectric forms, as it were, a stack that is perpendicular to the surface of the semiconductor substrate or the passivation region thereof, the sequence, that is to say, the stack direction, extending in the horizontal direction and the respective regions, namely the first and second electrodes and the dielectric provided between the latter running perpendicularly.
In an advantageous manner, the dielectric in each case has a ferroelectric and/or a paraelectric material or the like or is formed from such a material.
It is furthermore preferably provided that the capacitor configuration has, at least in part, a connected or chain structure of the capacitor devices. This form of the connection of the capacitor devices and the latters"" utilization of common electrode devices is particularly space-saving and, thus, supports the formation of the highest possible integration densities.
In accordance with still a further mode of the invention, to realize the chain structure discussed above, at least some of the capacitor devices are formed in a manner contact-connected by their respective first electrode device through a first contact element to the first electrode device of a first substantially directly spatially adjacent capacitor device and by their second electrode device through a second contact element to the second electrode device in the second substantially spatially directly adjacent capacitor device of the capacitor configuration.
The contact elements can also be referred to as contact or junction regions. Preferably, in this case, the first electrode devices and/or second electrode devices that are in each case contact-connected to one another in each case form a substantially contiguous, one-part and/or integral electrically conductive region. This can be done, for example, by forming the respective contact-connected electrode devices, for example, in the form of a contiguous metal region or the like. On the other hand, it is conceivable for the electrode devices that are contact-connected to one another to form in each case separate conductive, for example, metallic, regions that are contact-connected to one another through a respectively provided first or second contact element. An interaction of the electrodes with parts of the plug regions may also be provided.
For the contact connection and/or interconnection of the capacitor configuration and/or, in particular, of the capacitor devices, in particular, the electrode devices, in the semiconductor substrate or the like and/or in a covering layer or passivation layer and/or in the surface region thereof, a contact region or plug region is respectively provided, which is formed in a manner substantially electrically conductively contact-connected in each case, in particular, with the respective capacitor device, in particular, with the respective electrode device thereof. This means that the circuit underlying the semiconductor memory device, for example, in the form of a CMOS structure, is connected to the capacitor electrodes or electrode devices through the respective contact regions or plug regions. This is done, for example, by direct contact connection of the plug regions to the individual electrodes or to the first or contact elements provided, which connect the electrode devices to one another.
It is advantageously furthermore provided that the electrode devices are disposed and/or formed in each case substantially in a region in direct spatial proximity to the contact regions or plug regions, in particular, in a manner directly adjoining the latter and/or, in particular, directly above the latter on the surface region of the semiconductor substrate or a covering layer or passivation layer thereof.
The application and patterning of a dielectric is problematic, in principle, because a multiplicity of parameters must be optimized to realize desired electrical properties for the capacitor devices to be formed.
Accordingly, in accordance with still an additional mode of the semiconductor memory device according to the invention, it is provided that a barrier and/or insulation region for the dielectric, made of a substantially electrically insulating material, is provided between the dielectric and the region of the semiconductor substrate or the like and/or the passivation region and/or the surface region thereof. The material serves, on one hand, as mechanical contact layer and transition layer between the semiconductor surface or passivation surface and the dielectric. Furthermore, the electrical insulation of the dielectric from the semiconductor material and/or the passivation material continues to be ensured so that leakage currents are avoided to the greatest possible extent.
In such a case, the barrier and/or insulation region for the dielectric is optionally formed in a multilayer manner to achieve the functioning ascribed to it in a particularly favorable manner.
In accordance with a concomitant mode of the invention, at least the region facing the dielectric or the corresponding layer of the barrier and/or insulation region for the dielectric, that is to say, in particular, the surface region thereof, is formed as a nucleation layer or the like, to support and/or stabilize a desired structure, in particular, a crystal structure or the like, for the dielectric during processing and/or during operation of the semiconductor memory device. In particular, in this case, a crystal growth process is conceivable that is initiated on the surface region of the barrier and/or insulation region for the dielectric layer, that is to say, the nucleation step, and that, by virtue of its structure, controls and constrains a specific crystal geometry or crystal orientation during the production or during the growth and/or during heat treatment (after deposition) of the dielectric material.
Further aspects and advantages of the present invention emerge from the following remarks.
During the fabrication of ferroelectric capacitors for applications in nonvolatile semiconductor memories having a high integration density, a ferroelectric material is used as dielectric between the electrodes of a storage capacitor. This may involve materials such as SrBi2(Ta, Nb)2O9 (SBT or SBTN), Pb(Zr, Ti)O3 (PZT), or Bi4Ti3O12 (BTO) or the like, or slight modifications. It is also possible to use paraelectric materials, for example (BA, Sr)TiO3 (BST).
Because, after the deposition of the dielectric, the dielectric is subjected to a heat treatment process with regard to its crystal structure and its electromagnetic properties, the material for the electrodes should be able to withstand high temperatures in an oxygen-containing atmosphere. Noble metals or metallic oxides are, thus, appropriate. In particular, Pt, Pd, Ir, Rh, Ru, RuOx, IrOx, RhOx, SrRuO3, LSCO (LaSrCoOx), high-temperature (HT) superconductors (YBa2Cu3O7, . . . or the like can be used.
Conventional semiconductor memory devices and, in particular, ferroelectric semiconductor memories are disadvantageous to the effect that their integration density is critically limited by the minimum requirements with regard to the electrode areas. This is due to the fact that the electrodes are disposed in horizontal orientation with respect to the surface of the semiconductor substrate or its passivation region.
Furthermore, the electrode devices of the capacitors are disposed substantially two-dimensionally as a result.
The basic concept of the present invention is the formation of a three-dimensional and/or vertical structure for ferroelectric storage capacitors for FeRAM memory modules, in particular, of the chain type.
In such a case, vertical means that the electrodes of the storage capacitors are disposed vertically or running vertically in or with respect to the ferroelectric. A three-dimensional vertical capacitor is simple to miniaturize because in such a case exclusively the layer thicknesses that are physically to be minimally complied with are a limiting factor for the integration density. A vertically disposed storage capacitor, therefore, requires a particularly small space on the surface of the semiconductor substrate. Consequently, a 4F2 cell is conceivable in the case of the chain concept with a vertical three-dimensional capacitor, F being the minimum feature size that can be achieved.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating a semiconductor memory device, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.